Design-Reuse

Reusable Sequences in UVM

In this blog, I will be sharing the necessary steps one has to take while writing a sequence to make sure it can be reusable. Having developed sequences and tests in UVM, while using Verification IPs, ...
Semiconductor Engineering

Inside UVM, Take Two

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In ...
EDN

UVM Reactive agents verify with a handshake

UVM (Universal Verification Methodology) is widely used in creating object-oriented test environments. UVM provides two key benefits to verification engineers; one is reusability; the other is ...
Design-Reuse

Virtual Sequences in UVM: Why, How?

In my previous blog post, I discussed guidelines to create reusable sequences. Continuing on this thread, here I am going to talk about virtual sequences and the virtual sequencer. Common questions I ...
Semiconductor Engineering

Inside UVM

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t ...
Semiconductor Engineering

UVM: It’s Organized And Systematic

One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to ...
Design-Reuse

Reusable Sequences in UVM

In this blog, I describe the necessary steps one has to take while writing a sequence to make sure it can be reusable. Personally, I feel writing sequences is the most challenging part in verifying ...
Design-Reuse

Virtual Sequences in UVM: Why? How?

In my previous blog post, I talked about guidelines to create reusable sequences. Continuing on this thread, here I am going to talk about virtual sequences and the virtual sequencer. Common questions ...